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M74HC4094
8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
s
s
s
s
s
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HIGH SPEED : fMAX = 80 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4094
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HC4094B1R M74HC4094M1R T&R M74HC4094RM13TR M74HC4094TTR
DESCRIPTION The M74HC4094 is an high speed CMOS 8 BIT SIPO SHIFT LATCH REGISTER fabricated with silicon gate C2MOS technology. This device consists of an 8 bit shift register and an 8 bit latch with 3 state output buffer. Data is shifted serially trough the shift register on the positive going transition of the clock input signal. The output of the last stage (Qs) can be used to cascade several devices. Data on the Qs output is transferred to a second output (Qs') on the following negative transition of
the clock input signal. The data of each stage of the shift register is provided with a latch, which latches data on the negative going transition of the STROBE input signal. When the STROBE input is held high, data propagates through the latch to a 3-state output buffer. This buffer is enabled when OUTPUT ENABLE input is taken high. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
January 2003
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M74HC4094
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2 3 4, 5, 6, 7, 14, 13, 12, 11 9, 10 15 8 16 SYMBOL STROBE SERIAL IN CLOCK Q1 to Q7 QS Q'S OE GND Vcc NAME AND FUNCTION Strobe Input Serial Input Clock Input Parallel Outputs Serial Outputs Output Enable Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
PARALLEL OUTPUTS CK OE H H H L H L
X : Don't Care Z : High Impedance NC: No Change
SERIAL OUTPUTS Qs Q7 Q7 Q7 NC NC Q7 Qs' NC NC NC Q8 Q8 NC
ST H H L X H X
SI Q1 L H X X H X L H NC Z NC Z Qn Qn-1 Qn-1 NC Z NC Z
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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M74HC4094
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 C; derate to 300mW by 10mW/C from 65C to 85C
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M74HC4094
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 6.0 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 0.5 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 5 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 10 80 A A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
ICC
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M74HC4094
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25C Min. Typ. 30 8 7 92 26 20 65 19 15 75 20 16 58 16 13 35 16 13 16 66 80 17 7 6 28 6 6 30 7 5 45 10 8 Max. 75 15 13 200 40 34 150 30 26 160 32 27 150 30 26 150 30 26 4.8 24 28 75 15 13 75 15 13 75 15 13 100 20 17 0 0 0 95 19 16 95 19 16 95 19 16 125 25 21 0 0 0 Value -40 to 85C Min. Max. 95 19 16 250 50 43 190 38 32 200 40 34 190 38 32 190 38 32 4 20 24 110 22 19 110 22 19 110 22 19 145 29 25 0 0 0 -55 to 125C Min. Max. 115 23 20 300 60 51 225 45 38 240 48 41 225 45 38 225 45 38 ns Unit
tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - Qn) tPLH tPHL Propagation Delay Time (CLOCK - QS, Q'S) tPLH tPHL Propagation Delay Time (STROBE - Qn) tPZL tPZH High Impedance Output Enable Time tPHZ tPLZ High Impedance Output Disable Time fMAX Maximum Clock Frequency Minimum Pulse Width Minimum Pulse Width Minimum Set-up Time (SERIAL INPUT) Minimum Set-up Time (STROBE) Minimum Hold Time (SI, ST)
ns
ns
ns
ns
ns
6 30 35
MHz
tW(H) tW(L) tW(L)
ns
ns
ts
ns
ts
ns
th
ns
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M74HC4094
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25C Min. Typ. 5 140 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2(per FLIP/ FLOP)
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
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M74HC4094
WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CLOCK), SETUP AND HOLD TIMES (CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 2 :PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (STROBE), SETUP AND HOLD TIMES (STROBE)(f=1MHz; 50% duty cycle)
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M74HC4094
WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIMES(f=1MHz; 50% duty cycle)
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M74HC4094
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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M74HC4094
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 8 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.008 0.064 0.018 0.010
PO13H
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M74HC4094
TSSOP16 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
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M74HC4094
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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